arch Architecture Reference

Components
FIFO_FM0	<Entity FIFO_FM0>
sender_controller	<Entity sender_controller>
signal_generator

Signals
encoder_ended	std_logic := ' 0 '
generator_ended	std_logic := ' 0 '
generator_out	std_logic := ' 0 '
encoder_out	std_logic := ' 0 '
signal_generator_ended	std_logic := ' 0 '
start_encoder	std_logic := ' 0 '
start_generator	std_logic := ' 0 '
mux	std_logic := ' 0 '

Instantiations
controller	sender_controller <Entity sender_controller>
generator	Signal_Generator <Entity Signal_Generator>
fifo_fm0_c	FIFO_FM0 <Entity FIFO_FM0>

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The documentation for this class was generated from the following file:

• fpga/RTL/sender.vhd