Signal_Generator Entity Reference

https://github.com/pfeinsper/21b-indago-rfid-conformance-tester/blob/main/fpga/RTL/signal_generator.vhd More...

Inheritance diagram for Signal_Generator:

Entities
arch	architecture

Libraries
ieee

Use Clauses
std_logic_1164
numeric_std

Generics
tari_width	natural := 16
	Bits reserved for the TARI time parameter.
pw_width	natural := 16
	Bits reserved for the PW time parameter.
delimiter_width	natural := 16
	Bits reserved for the delimiter time parameter.
RTcal_width	natural := 16
	Bits reserved for the receiver transmitter callibration time parameter.
TRcal_width	natural := 16
	Bits reserved for the transmitter receiver callibration time parameter.

Ports
clk	in	std_logic
		Clock input.
rst	in	std_logic
		Reset high.
enable	in	std_logic
		Enable high.
start_send	in	std_logic
		Flag indicates a new encoded packet must be sent.
is_preamble	in	std_logic
		Flag indicates preamble if high; framesync if low.
tari	in	std_logic_vector ( tari_width - 1 downto 0 )
		Time parameter.
pw	in	std_logic_vector ( pw_width - 1 downto 0 )
		PW parameter.
delimiter	in	std_logic_vector ( delimiter_width - 1 downto 0 )
		Delimiter parameter.
RTcal	in	std_logic_vector ( RTcal_width - 1 downto 0 )
		Receiver transmitter callibration parameter.
TRcal	in	std_logic_vector ( TRcal_width - 1 downto 0 )
		Transmitter receiver callibration parameter.
has_ended	out	std_logic := ' 0 '
		Flag indicates packet has been sent.
data_out	out	std_logic := ' 0 '
		Generator - preamble or framesync - signal.

Detailed Description

https://github.com/pfeinsper/21b-indago-rfid-conformance-tester/blob/main/fpga/RTL/signal_generator.vhd

 This component generates the preamble or framesync flag when requested

Member Data Documentation

ieee

ieee

Library

\signal_generator.vhd

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The documentation for this class was generated from the following file:

• fpga/RTL/signal_generator.vhd