arch Architecture Reference

Processes
delimiter_generator	( clk , rst , enable )

Types
state_type_generator	( g_wait , g_delimiter , g_data0 , g_data0_PW , g_RTcal , g_RTcal_PW , g_TRcal , g_TRcal_PW )

Signals
tari_value	integer := 0
pw_value	integer := 0
delimiter_value	integer := 0
RTcal_value	integer := 0
TRcal_value	integer := 0
state_generator	state_type_generator := g_wait

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The documentation for this class was generated from the following file:

• fpga/RTL/signal_generator.vhd