sender_controller Entity Reference

https://github.com/pfeinsper/21b-indago-rfid-conformance-tester/blob/main/fpga/RTL/sender_controller.vhd More...

Inheritance diagram for sender_controller:

Entities
arch	architecture

Libraries
ieee

Use Clauses
std_logic_1164
numeric_std

Ports
clk	in	std_logic
		Clock input.
rst	in	std_logic
		Reset high.
enable	in	std_logic
		Enable high.
start	in	std_logic
		Flag indicates a new command must be encoded and sent.
signal_generator_ended	in	std_logic
		Flag high if preamble or framesync finished.
encoder_ended	in	std_logic
		Flag high if encoder has no more data to send.
has_gen	in	std_logic
		Flag high if using the preamble or framesync.
clr_finished_sending	in	std_logic
		Clears the finished_sending flag.
mux	out	std_logic
		Flag control mux output.
finished_sending	out	std_logic := ' 0 '
		Flag high if sender has no more data to send.
start_encoder	out	std_logic := ' 0 '
		Flag high to start the encoder.
start_generator	out	std_logic := ' 0 '
		Flag high to start preamble or framesync.

Detailed Description

https://github.com/pfeinsper/21b-indago-rfid-conformance-tester/blob/main/fpga/RTL/sender_controller.vhd

 This component is responsible for indicating to the other sender components if the data should be encoded or sent, since the TARI controls the rate at which encoded packets can be sent

Member Data Documentation

ieee

ieee

Library

\sender_controller.vhd

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The documentation for this class was generated from the following file:

• fpga/RTL/sender_controller.vhd