sender Entity Reference

https://github.com/pfeinsper/21b-indago-rfid-conformance-tester/blob/main/fpga/RTL/sender.vhd More...

Inheritance diagram for sender:

Collaboration diagram for sender:

Entities
arch	architecture

Libraries
IEEE

Use Clauses
std_logic_1164
std_logic_unsigned
numeric_std
all

Generics
data_width	natural := 26
	Size of the data inside a packet sent between components.
tari_width	natural := 16
	Bits reserved for the TARI time parameter.
pw_width	natural := 16
	Bits reserved for the PW time parameter.
delimiter_width	natural := 16
	Bits reserved for the delimiter time parameter.
RTcal_width	natural := 16
	Bits reserved for the receiver transmitter callibration time parameter.
TRcal_width	natural := 16
	Bits reserved for the transmitter receiver callibration time parameter.
mask_width	natural := 6
	Size of the mask that indicates how many bits of the packet are in use.

Ports
clk	in	std_logic
		Clock input.
clr_finished_sending	in	std_logic
		Clears the finished_sending flag.
enable	in	std_logic
		Enable high.
rst	in	std_logic
		Reset high.
finished_sending	out	std_logic
		Flag that indicates the packet has been sent.
clear_fifo	in	std_logic
		Clears all data from the FIFO.
fifo_write_req	in	std_logic
		Flag to write new data on the FIFO.
is_fifo_full	out	std_logic
		Flag that indicates if the FIFO has run out of space.
usedw	out	std_logic_vector ( 7 downto 0 )
		Number of valid packets in the FIFO.
has_gen	in	std_logic
		Flag high if using the preamble or framesync.
start_controller	in	std_logic
		Flag high to start sending the data.
is_preamble	in	std_logic
		Flag indicates preamble if high; framesync if low.
tari	in	std_logic_vector ( tari_width - 1 downto 0 )
		Time parameter.
pw	in	std_logic_vector ( pw_width - 1 downto 0 )
		PW parameter.
delimiter	in	std_logic_vector ( delimiter_width - 1 downto 0 )
		Delimiter parameter.
RTcal	in	std_logic_vector ( RTcal_width - 1 downto 0 )
		Receiver transmitter callibration parameter.
TRcal	in	std_logic_vector ( TRcal_width - 1 downto 0 )
		Transmitter receiver callibration parameter.
data	in	std_logic_vector ( 31 downto 0 )
		Packet to be encoded and sent to the TAG.
q	out	std_logic
		Modulated in FM0 out signal.

Detailed Description

https://github.com/pfeinsper/21b-indago-rfid-conformance-tester/blob/main/fpga/RTL/sender.vhd

 This component receives individual packets from the Avalon Interface and stores them in a FIFO until each packet is ready to be encoded. Currently only supports the FM0 encoding.
 After this, it is also responsible for sendind the encoded packets to the TAG, while respecting the restrictions of the preamble, framesync and TARI.

Member Data Documentation

IEEE

IEEE

Library

\sender.vhd

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The documentation for this class was generated from the following file:

• fpga/RTL/sender.vhd