https://github.com/pfeinsper/21b-indago-rfid-conformance-tester/blob/main/fpga/RTL/fifo_fm0.vhd More...
Inheritance diagram for FIFO_FM0:
Collaboration diagram for FIFO_FM0:
Entities | |
| arch | architecture |
Libraries | |
| ieee | |
Use Clauses | |
| std_logic_1164 | |
| numeric_std | |
Generics | |
| data_width | natural := 26 |
| Size of the data inside a packet sent between components. | |
| tari_width | natural := 16 |
| Bits reserved for the TARI time parameter. | |
| mask_width | natural := 6 |
| Size of the mask that indicates how many bits of the packet are in use. | |
Ports | ||
| clk | in | std_logic |
| Clock input. | ||
| rst_fm0 | in | std_logic |
| Reset high. | ||
| enable_fm0 | in | std_logic |
| Enable high. | ||
| encoder_ended | out | std_logic |
| Flag high if encoder has no more data to send. | ||
| clear_fifo | in | std_logic |
| Clears all data from the FIFO. | ||
| fifo_write_req | in | std_logic |
| Flag to write new data on the FIFO. | ||
| is_fifo_full | out | std_logic |
| Flag that indicates if the FIFO has run out of space. | ||
| usedw | out | std_logic_vector ( 7 downto 0 ) |
| Number of valid packets in the FIFO. | ||
| tari | in | std_logic_vector ( tari_width - 1 downto 0 ) |
| Time parameter. | ||
| data | in | std_logic_vector ( 31 downto 0 ) |
| Packet to be encoded and sent to the TAG. | ||
| q | out | std_logic |
| Modulated in FM0 out signal. | ||
Detailed Description
https://github.com/pfeinsper/21b-indago-rfid-conformance-tester/blob/main/fpga/RTL/fifo_fm0.vhd
Component that integrates the FIFO with the FM0 encoder.
Member Data Documentation
◆ ieee
|
Library |
\fifo_fm0
The documentation for this class was generated from the following file:
- fpga/RTL/fifo_fm0.vhd
