arch Architecture Reference

Processes
PROCESS_0	( clk )
aa	( clk , fifo_write_req )

Components
sender	<Entity sender>
receiver	<Entity receiver>

Signals
reg_settings	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
reg_status	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
reg_send_tari	std_logic_vector ( 15 downto 0 )
reg_send_tari_101	std_logic_vector ( 15 downto 0 )
reg_send_tari_099	std_logic_vector ( 15 downto 0 )
reg_send_tari_1616	std_logic_vector ( 15 downto 0 )
reg_send_tari_1584	std_logic_vector ( 15 downto 0 )
reg_send_pw	std_logic_vector ( 15 downto 0 )
reg_send_delimiter	std_logic_vector ( 15 downto 0 )
reg_send_RTcal	std_logic_vector ( 15 downto 0 )
reg_send_TRcal	std_logic_vector ( 15 downto 0 )
fifo_data_in	std_logic_vector ( data_size - 1 downto 0 )
fifo_write_req	std_logic := ' 0 '
fifo_write	std_logic := ' 0 '
receiver_data_out	std_logic_vector ( 31 downto 0 )
reg_read_usedw_receiver	std_logic_vector ( 7 downto 0 )
reg_read_usedw_sender	std_logic_vector ( 7 downto 0 )
pin_tx	std_logic := ' 0 '
pin_rx	std_logic := ' 0 '

Instantiations
rfid_sender	sender <Entity sender>
rfid_receiver	receiver <Entity receiver>

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The documentation for this class was generated from the following file:

• fpga/RTL/rfid.vhd