rfid Entity Reference

https://github.com/pfeinsper/21b-indago-rfid-conformance-tester/blob/main/fpga/RTL/rfid.vhd More...

Inheritance diagram for rfid:

Collaboration diagram for rfid:

Entities
arch	architecture

Libraries
IEEE

Use Clauses
std_logic_1164
std_logic_unsigned
numeric_std
all

Generics
data_width	natural := 26
	Size of the data inside a packet sent between components.
tari_width	natural := 16
	Bits reserved for the TARI time parameter.
mask_width	natural := 6
	Size of the mask that indicates how many bits of the packet are in use.
data_size	natural := 32
	Size of the packets including the mask.

Ports
clk	in	std_logic
		Clock input.
rst	in	std_logic
		Reset high.
avs_address	in	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
		Points to the specific address in the memory bank.
avs_read	in	std_logic := ' 0 '
		Indicates a read request if high.
avs_readdata	out	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
		Data being read from the avs_address.
avs_write	in	std_logic := ' 0 '
		Indicates a write request if high.
avs_writedata	in	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
		Data being written to the avs_address.
rfid_tx	out	std_logic
		Reader output.
rfid_rx	in	std_logic
		Reader input.

Detailed Description

https://github.com/pfeinsper/21b-indago-rfid-conformance-tester/blob/main/fpga/RTL/rfid.vhd

Project top level, instantiates the sender, receiver and Avalon Interface. This component encopasses the whole project. Instantiating the Avalon Interface allows for communication between hardware and software, or, in other words, the NIOS II and the IP RFID.

Member Data Documentation

IEEE

IEEE

Library

\rfid.vhd

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The documentation for this class was generated from the following file:

• fpga/RTL/rfid.vhd