receiver Entity Reference

https://github.com/pfeinsper/21b-indago-rfid-conformance-tester/blob/main/fpga/RTL/receiver.vhd More...

Inheritance diagram for receiver:

Collaboration diagram for receiver:

Entities
arch	architecture

Libraries
IEEE

Use Clauses
std_logic_1164
std_logic_unsigned
numeric_std
all

Generics
data_width	natural := 26
	Size of the data inside a packet sent between components.
tari_width	natural := 16
	Bits reserved for the TARI time parameter.
mask_width	natural := 6
	Size of the mask that indicates how many bits of the packet are in use.

Ports
clk	in	std_logic
		Clock input.
rst	in	std_logic
		Reset high.
enable	in	std_logic
		Enable high.
data_DUT	in	std_logic
		Encoded data received from the TAG.
tari_101	in	std_logic_vector ( tari_width - 1 downto 0 )
		1% above tari limit
tari_099	in	std_logic_vector ( tari_width - 1 downto 0 )
		1% below tari limit
tari_1616	in	std_logic_vector ( tari_width - 1 downto 0 )
		1% above 1.6 tari limit
tari_1584	in	std_logic_vector ( tari_width - 1 downto 0 )
		1% below 1.6 tari limit
clr_err_decoder	in	std_logic
		Flag clears decoder error.
err_decoder	out	std_logic
		Flag decoder error indicator.
rdreq	in	std_logic
		Flag FIFO read request.
sclr	in	std_logic
		Flag FIFO clear.
empty	out	std_logic
		Flag that indicates if the FIFO has no more data stored.
full	out	std_logic
		Flag that indicates if the FIFO has run out of space.
data_out_fifo	out	std_logic_vector ( 31 downto 0 )
		Packet sent from the FIFO to the Avalon Interface.
usedw	out	std_logic_vector ( 7 downto 0 )
		Number of valid packets in the FIFO.

Detailed Description

https://github.com/pfeinsper/21b-indago-rfid-conformance-tester/blob/main/fpga/RTL/receiver.vhd

 The data is received bit by bit, and thus needs to be first gouped in pairs, in order to be decoded, since the TAG also uses the FM0 encoding.
 After this, the decoded bits are stored in a FIFO until the packet is complete and ready to be sent back to the NIOS II.
 If the command ends before the packet is completed, a mask is sent to denote which bits of the packet are actually data.

Member Data Documentation

IEEE

IEEE

Library

\receiver.vhd

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The documentation for this class was generated from the following file:

• fpga/RTL/receiver.vhd