arch Architecture Reference

Processes
pulse_generator	( rst , clk , rdreq )

Components
FM0_decoder	<Entity FM0_decoder>
fifo_32_32
package_constructor	<Entity package_constructor>

Signals
data_out_pc	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
write_request	std_logic := ' 0 '
data_ready	std_logic := ' 0 '
eop	std_logic := ' 0 '
data_out_decoder	std_logic := ' 0 '
rdreq_pulse	std_logic := ' 0 '
clr_eop	std_logic := ' 0 '

Instantiations
fifo	fifo_32_32
pack_const	package_constructor <Entity package_constructor>
decoder	FM0_decoder <Entity FM0_decoder>

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The documentation for this class was generated from the following file:

• fpga/RTL/receiver.vhd