FM0_decoder Entity Reference

https://github.com/pfeinsper/21b-indago-rfid-conformance-tester/blob/main/fpga/RTL/FM0_decoder.vhd More...

Inheritance diagram for FM0_decoder:

Entities
arch	architecture

Libraries
ieee

Use Clauses
std_logic_1164
numeric_std

Generics
tari_width	natural := 16
	Bits reserved for the TARI time parameter.

Ports
clk	in	std_logic
		Clock input.
rst	in	std_logic
		Reset high.
enable	in	std_logic
		Enable high.
clr_err	in	std_logic
		Flag clears error indicator.
clr_eop	in	std_logic
		Flag clears EOP indicator.
err	out	std_logic := ' 0 '
		Flag high if error ocurred.
eop	out	std_logic := ' 0 '
		Flag high if EOP detected.
tari_101	in	std_logic_vector ( tari_width - 1 downto 0 )
		1% above tari limit
tari_099	in	std_logic_vector ( tari_width - 1 downto 0 )
		1% below tari limit
tari_1616	in	std_logic_vector ( tari_width - 1 downto 0 )
		1% above 1.6 tari limit
tari_1584	in	std_logic_vector ( tari_width - 1 downto 0 )
		1% below 1.6 tari limit
data_in	in	std_logic := ' 0 '
		Encoded bits from the TAG.
data_ready	out	std_logic := ' 0 '
		Flag indicates encoded bit is valid.
data_out	out	std_logic := ' 0 '
		Decoded bit going to the package constructor.

Detailed Description

https://github.com/pfeinsper/21b-indago-rfid-conformance-tester/blob/main/fpga/RTL/FM0_decoder.vhd

For further explanation on how this decoding is done, check the EPC-GEN2 documentation - https://www.gs1.org/sites/default/files/docs/epc/Gen2_Protocol_Standard.pdf

Member Data Documentation

ieee

ieee

Library

\FM0_decoder.vhd

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The documentation for this class was generated from the following file:

• fpga/RTL/FM0_decoder.vhd