arch Architecture Reference

Processes
decoder_controller	( clk , rst , enable )
decoder_data	( clk , rst , enable )
counter	( clk , rst )

Types
state_type_controller	( c_wait , c_decode )
state_type_decoder	( d_wait , d_start_counter , d_start_counter2 , d_wait_counter , d_wait_counter2 , d_check_counter , d_check_counter2 , d_continue_counter , d_error , d_pass_1_01_tari , d_counter_cs , d_end )

Signals
tari_1616_value	integer
tari_1584_value	integer
tari_1010_value	integer
tari_0990_value	integer
tari_0505_value	integer
tari_0495_value	integer
data_receiver_start	std_logic := ' 0 '
data_receiver_end	std_logic := ' 0 '
clock_start	std_logic := ' 0 '
clear_counter	std_logic := ' 0 '
prev_bit_c	std_logic := ' 0 '
prev_bit_d	std_logic := ' 0 '
clocks_counted	integer range 0 to 500000000
state_controller	state_type_controller := c_wait
state_decoder	state_type_decoder := d_wait

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The documentation for this class was generated from the following file:

• fpga/RTL/FM0_decoder.vhd