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21b-indago-rfid-conformance-tester
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https://github.com/pfeinsper/21b-indago-rfid-conformance-tester/blob/main/fpga/RTL/package_constructor.vhd More...

Entities | |
| arch | architecture |
Libraries | |
| ieee | |
Use Clauses | |
| std_logic_1164 | |
| numeric_std | |
Generics | |
| data_width | natural := 26 |
| Size of the data inside a packet sent between components. | |
| mask_width | natural := 6 |
| Size of the mask that indicates how many bits of the packet are in use. | |
Ports | ||
| clk | in | std_logic |
| Clock input. | ||
| rst | in | std_logic |
| Reset high. | ||
| data_ready | in | std_logic := ' 0 ' |
| Flag indicates new data is coming from the FM0_decoder. | ||
| data_in | in | std_logic := ' 0 ' |
| Data received from the FM0_decoder. | ||
| eop | in | std_logic := ' 0 ' |
| Flag indicates end of package. | ||
| write_request_out | out | std_logic := ' 0 ' |
| Flag request to write data on the FIFO. | ||
| data_out | out | std_logic_vector ( ( data_width + mask_width ) - 1 downto 0 ) |
| Packet out to the FIFO. | ||
| clr_eop | out | std_logic := ' 0 ' |
| Flag clears EOP. | ||
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Library |
\package_constructor.vhd
1.8.17