arch Architecture Reference

Processes
fm0_controller	( clk , rst , enable )
data_sender	( clk , rst , enable , data_sender_end )
half_tari	( clk , rst , enable )
full_tari	( clk , rst , enable )
wait_CS_tari	( clk , rst , enable )

Types
state_type_controller	( c_wait , c_wait_send , c_request , c_wait_tari_CS , c_start_send , c_wait_request )
state_type_sender	( s_wait , s_send_s1 , s_send_s2 , s_send_s2_part2 , s_send_s3 , s_send_s3_part2 , s_send_s4 , s_end )

Signals
data	std_logic_vector ( data_width - 1 downto 0 )
mask	std_logic_vector ( mask_width - 1 downto 0 )
mask_value	integer
tari_value	integer
data_sender_start	std_logic := ' 0 '
data_sender_end	std_logic := ' 0 '
half_tari_start	std_logic := ' 0 '
half_tari_end	std_logic := ' 0 '
full_tari_start	std_logic := ' 0 '
full_tari_end	std_logic := ' 0 '
tari_CS_start	std_logic := ' 0 '
tari_CS_end	std_logic := ' 0 '
state_controller	state_type_controller := c_wait
state_sender	state_type_sender := s_wait

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The documentation for this class was generated from the following file:

• fpga/RTL/FM0_encoder.vhd