FM0_encoder Entity Reference

https://github.com/pfeinsper/21b-indago-rfid-conformance-tester/blob/main/fpga/RTL/FM0_encoder.vhd More...

Inheritance diagram for FM0_encoder:

Entities
arch	architecture

Libraries
ieee

Use Clauses
std_logic_1164
numeric_std

Generics
data_width	natural := 26
	Size of the data inside a packet sent between components.
tari_width	natural := 16
	Bits reserved for the TARI time parameter.
mask_width	natural := 6
	Size of the mask that indicates how many bits of the packet are in use.

Ports
clk	in	std_logic
		Clock input.
rst	in	std_logic
		Reset high.
enable	in	std_logic
		Enable high.
finished_sending	out	std_logic
		Flag high if sender has no more data to send.
tari	in	std_logic_vector ( tari_width - 1 downto 0 )
		Time parameter.
is_fifo_empty	in	std_logic
		Flag that indicates if the FIFO has no more data.
data_in	in	std_logic_vector ( ( data_width + mask_width ) - 1 downto 0 )
		packet with 26 data bits and 6 mask bits - format ddddddddddddddddddddddddddmmmmmm
request_new_data	out	std_logic
		Flag high if requests new packet to encode and send.
data_out	out	std_logic := ' 0 '
		Modulated in FM0 out signal.

Detailed Description

https://github.com/pfeinsper/21b-indago-rfid-conformance-tester/blob/main/fpga/RTL/FM0_encoder.vhd

For further explanation on how this encoding is done, check the EPC-GEN2 documentation - https://www.gs1.org/sites/default/files/docs/epc/Gen2_Protocol_Standard.pdf

Member Data Documentation

ieee

ieee

Library

\FM0_encoder.vhd

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The documentation for this class was generated from the following file:

• fpga/RTL/FM0_encoder.vhd